1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, example embodiments of the present invention relate to a semiconductor device comprising metal gate patterns and a related method of manufacture.
This application claims priority to Korean Patent Application No. 2005-0030179, filed on Apr. 12, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
In general, semiconductor devices comprise gate patterns, each of which comprises a gate insulation layer. Recent developments have produced a gate insulation layer formed from a material having a relatively high dielectric constant and having, therefore, a relatively small equivalent oxide thickness (EOT). This improvement significantly decreases leakage current between the gate pattern and an associated channel region.
However, when a polysilicon layer is formed directly on a gate insulation layer formed from a material having a relatively high dielectric constant, a fermi level pinning phenomenon may occur at an interface between the gate insulation layer and the polysilicon layer. This phenomenon essentially prevents charge carriers within the polysilicon layer from properly migrating. Thus, it may not be easy to control the flatband voltage (Vfb) of the constituent semiconductor device which is proportional to a threshold voltage.
On the other hand, forming a gate conductive layer by depositing a metal layer on the gate insulation layer yields many benefits. For example, the fermi level pinning phenomenon may be alleviated when a metal gate conductive layer is used. Additionally, an increased EOT—which is often generated by a poly depletion effect in a gate conductive layer formed from polysilicon—may also be avoided when the gate conductive layer is formed from metal. Further, charge trapping effects and remote charge scattering effects may be alleviated, thereby improving the operation speed of the constituent semiconductor device. Additionally, a metal gate conductive layer may also serve as a barrier layer preventing an undesired diffusion of impurities during implantation processes used to form source/drain regions of the semiconductor device.
Recently developed gate patterns comprise a gate insulation layer formed from a material having a high dielectric constant, and a gate conductive layer formed from metal and polysilicon. Methods of forming such a gate pattern are disclosed, for example, in U.S. Patent Application Publication No. 2004/0106249, U.S. Pat. No. 6,518,106, and U.S. Pat. No. 6,552,377.
U.S. Pat. No. 6,552,377 discloses a method of forming gate conductive layers for a PMOS region and an NMOS region, wherein the respective gate conductive layers comprise different metals. However, this method suffers from the disadvantage of forming the gate patterns through a relatively complicated process.
U.S. Pat. No. 6,518,106 discloses a method of forming gate conductive layers in an NMOS region and a PMOS region, wherein one of the gate conductive layers is formed from polysilicon and metal, and the other is formed from polysilicon. While this method forms gate conductive layers using a relatively simple process, the non-metal, gate conductive layer often suffers from one or more of the foregoing problems.
Clearly, the gate patterns for NMOS and PMOS regions should have different work functions to optimize performance of the respective active devices. In one attempt to provide gate patterns having satisfactory work functions, U.S. Patent Application Publication No. 2004/0106249 discloses a method of forming gate conductive layers, wherein the respective gate patterns for the NMOS and PMOS regions are formed from an identical metal layer, but with different thicknesses of the metal layer within the gate patterns. Therefore, according to this method, the gate conductive layer is formed by a relatively simple process, the respective gate patterns for the NMOS and PMOS regions have the advantage of being formed from both metal and polysilicon, and the respective gate patterns for the NMOS and PMOS regions have different work functions—as defined by the different thicknesses of the conductive layers within the respective gate patterns.
However, in the method disclosed in U.S. Patent Application Publication No. 2004/0106249, the work functions of the gate patterns are directly dependent upon only the thickness of the gate patterns. Unfortunately, this approach to gate pattern formation is limited in the range of work functions achievable in the respective NMOS and PMOS regions. Further, the exact work functions for the NMOS and PMOS regions may not be finely adjusted to a degree required for contemporary semiconductor device designs.